Automatic Verification of Arithmetic Circuits in RTL using Term Rewriting Systems
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چکیده
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منابع مشابه
Automatic Verification of Arithmetic Circuits using Step-wise Refinement of Term Rewriting Systems
This paper presents a novel technique for proving the correctness of arithmetic circuit designs described at the Register Transfer Level (RTL). The technique begins with the automatic translation of circuits from a Verilog RTL description into a Term Rewriting System (TRS). We prove the correctness of the designs via an equivalence proof between TRSs for the implementation circuit design and a ...
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